1. Field of the Invention
This invention relates to a semiconductor memory device and a preparation of the same, and more particularly to an improvement of a Static Random Access Memory cell (called hereunder a SRAM cell).
2. Description of the Related Art
Recently, a SRAM cell with a high load resistor is widely used, which comprises, as shown in FIG. 10(a), four transistors (Q1 to Q4) and two high load resistors (R1 and R2) , wherein access transistors Q1 and Q2 are each connected with respective bit lines (BL and BL) at their nodes of equivalent storage capacity. The equivalent storage capacity is provided by a flip flop comprising two inverters which are connected with each other and each includes specific transistors Q3 and Q4 and load resistors R1 and R2, respectively. As shown in FIG. 10(b), transistor 32 (Q1, Q2, Q3, Q4) is a bulk device formed in a semiconductor substrate 31. For a reduced area and high density, load resistor 34a (R1, R2) is defined in a polysilicon layer 34 which is deposited on the bulk device, having a dielectric 33 therebetween.
In recent years, a cell structure using thin film MOS transistor in place of the resistor has been proposed and is so constructed that a lower transistor layer and a polysilicon active layer 41 commonly have the same gate electrode 40 placed therebetween.
Problems involved in the conventional SRAM cells including the above two kinds of cell structure will be detailed hereunder (1) For applications requiring Static Access Memories to operate with batteries, it is essential to have a very low standby power dissipation and a 1.mu.A total standby current should be specified. For operation of a SRAM cell of a polysilicon load resistor type with a large bit density more than 1 Megabit, it, therefore, is essential to have a very high load resistance in an order of 10.sup.13 ohm, assuming that source voltage is 3 to 5V. It is technically hard to obtain such value of resistance with high accuracy as the device is microminiaturized. Also, in use of the above high load resistor, current to be supplied therein is very low as about 3.times.10.sup.-13 A which results in limited noise margin, increase of soft error and the like as referred to hereunder. (2) In an operation state of a SRAM, a memory cell is connected with a bit line of a different potential from those at the cell node through an access transistor in a read-out cycle, thereby causing an electric charge sharing between the bit lines and the memory cell. As a result, potential of the memory cell which corresponds to a voltage close to the power supply voltage V.sub.DD in "1" state lowers to a value close to the voltage at the bit line since the bit line is far higher in capacity than the memory cell.
The load device for a memory cell (NOTE: Polysilicon resistor in the conventional cells}serves for supplying electric charge for restoring potential of memory cell storage node after read-out to an initial potential. The restoration time in this case is proportional to the current to be supplied by the load device and the time constant on recharge is represented by the following equation.
______________________________________ T = C.sub.N xR C.sub.N : Equivalent capacity of memory cell node (5 to 10 fF for 1 MSRAM) R: Resistance of high load resistor ______________________________________
The time constant T on recharge is 0.1 sec when R=10.sup.13 ohm. The mean time interval to a next access of memory cell is usually less than 1 msec and the cell voltage is not sufficiently restored within that time, whereby the cell is sensitive to disturbance by noise to have decreased noise margin. (3) Next, a problem of soft error by .alpha. rays will be detailed As the memory cell is microminiaturized, its storage capacity is reduced, thereby soft error by .alpha. rays is likely to occur. Critical electric charge to induce breakage of stored data is represented by the following equation by using the simple circuit model shown in FIG. 9. EQU Q.sub.cri =V.sub.h xC.sub.N / (1-I.sub.load / I.sub.60 )
V.sub.h : Voltage of a node which stores "1" upon application of .alpha. rays
C.sub.N : Equivalent storage capacity of memory cell
I.sub.load : Current to be supplied from load device
I.sub..alpha. : .alpha. rays inducing current
In a SRAM cell with a high load resistor, I.sub.load &lt;&lt;I.sub..alpha., and the mean value of V.sub.h is lower than supply voltage V.sub.DD as referred at the item (3) and the value of Q.sub.crit becomes lower. As a result, soft error resistance particularly in a high speed operation of the device is deteriorated. (4) A memory cell using polysilicon MOS transistor as load devices is able to allow a higher ON current in comparison with that of the high load resistor type, thereby realizing a largely shortened recharge time and improved stability of the memory device. Hence, this technique is effective for constituting SRAM having high noise margin at a high speed operation and a very low standby power dissipation. However, in the known SRAM using polysilicon MOS transistor, the channel regions of the transistors are defined by the use of a photoresist mask, whereby it is difficult to align channel regions with a gate electrode underlying them, particularly for transistors in submicron size. In detail, in a memory cell wherein a bulk transistor and a polysilicon transistor commonly have the same gate electrode 40, when the bulk NMOS transistor is of the minimum channel length L.sub.n as shown in FIG. 11(c), the alignment registration tolerance DM is approximately L.sub.n /2. Hence, the substantial channel length of the polysilicon MOS transistor will vary between 0 and L.sub.n, thereby inducing non-uniformity in property of the cells. This results in great limitation for decreasing the size of cells and difficulty for producing operable memory devices.